IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of these results with the IC interconnect resistance and capacitance models significantly complicates most IC design and verification methodologies. In this tutorial paper we will review some of the analysis and verification problems associated with on–chip inductance, and present a subset of recent results for partially addressing the challenges which lie ahead.

Due to the global nature of inductive coupling, extracted inductance models come in various forms and are derived using several simplifying approximations. For IC inductance extraction the models are generally either in the form of port inductances based on simplified current path assumptions, or described by a complete partial inductance matrix. For certain regular, overdesigned structures, there is also the possibility of a 2D (two–dimensional) infinite line approximation model.

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